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The System Level Design R&D team at Synopsys has embarked on a mission to reduce pain points of System Data Observability through unique and intuitive dashboards, AI/ML driven workflows and descriptive & predictive analytics. Do you have a passion for quality and a keen eye for details Are you excited about the latest advancements in FPGA and hardware emulation Can you write RTL and C++ testbenches Then this role is for you!
In this role,
Responsibilities:
- Craft and execute comprehensive test plans specifically around hardware emulation leveraging RTL and testbench skills.
- Meticulously analyze test results to pinpoint discrepancies or potential issues.
- Proactively report identified issues to relevant stakeholders.
- Familiarity with scripting languages like Python to automate tasks on testing.
- Stay abreast of cutting-edge advancements in hardware emulation methodologies.
Qualification:
- BE / B. Tech / M. Tech in Computer Science or Electronics with 3+ Years of relevant experience.
- Exposure in hardware validation or emulation.
Must-have Skills:
- Capable to implement hardware blocks in Verilog.
- Capable to create and understand complex testbenches.
- Good practical knowledge in C/C++ and Python.
- Good understanding of UVM/C++ testbenches.
- Good understanding of transactors and monitors.
- Excellent communication (written and verbal) and teamwork abilities to collaborate effectively with stakeholders.
Good-to-have Skills:
- Good understanding of DPI concept.
- Good understanding of speed adaptors.
